CV

Senior Cyber Engineer

MITRE Corporation

Building automated tooling for software supply-chain verification, secure system architecture analysis, and Multi-Level Security prototyping.

• Developed a modular, containerized framework for automated software supply-chain verification, extending TruffleHog to improve secret-scanning and dependency-analysis coverage across source repositories.
• Authored technical documentation and conducted architectural analyses of processor (RISC/CISC) and system design trade-offs to support modernization and performance optimization decisions.
• Led the design and deployment of an automated, non-source-artifact assessment pipeline that enables stakeholders to assess contractor proficiency without requiring proprietary source code.
• Co-led the architectural design and rapid prototyping of containerized Multi-Level Security (MLS) environments. Developed MVPs to validate robust data protection, labeling challenges, and cross-classification data sharing, directly informing trade-space evaluations for critical federated systems.
• Directed automated Infrastructure-as-Code (IaC) analysis workflows and engineered headless system modeling templates (e.g., Cameo), enabling the programmatic extraction of architectural insights from high-level artifacts to conduct predictive risk assessments.

Research Assistant

Virginia Tech

Ph.D. research with Dr. Binoy Ravindran on compiler- and binary-level security: control-flow integrity, ARM Memory Tagging Extension integration, and automated data compartmentalization.

• Designed and deployed compiler- and binary-level security mechanisms to enforce control-flow integrity and automated data compartmentalization across untrusted code modules.
• Integrated the ARM Memory Tagging Extension (MTE) into a compiler toolchain, strengthening runtime memory safety and fault isolation.
• Implemented static and dynamic taint analysis to identify sensitive data paths and compartmentalization targets, automatically rewriting assembly code to isolate protected data regions.

Software Engineer

Raytheon

Documentation compliance for unclassified deliverables while clearance was processing.

• Supported documentation compliance for unclassified deliverables pending clearance activation.

Teaching Assistant

Penn State University

• Taught CMPSC 122: Intermediate Programming and led weekly discussion sessions.

Research Assistant

Penn State University

Advisor: Dr. Swaroop Ghosh

• Researched hardware security and reverse-engineering countermeasures using transistor-level camouflaging and logic obfuscation.

Research Assistant

University of South Florida

Advisor: Dr. Swaroop Ghosh

• Researched hardware security primitives leveraging CMOS and spintronic memory technologies, exploring MTJ-based techniques to improve PUF stability and STT-MRAM robustness against magnetic and thermal attacks.

Undergraduate Intern

Intel

• Developed analytics modules for the AIM Suite project to measure customer engagement with in-store digital displays.
• Evaluated MongoDB integration for production deployment, assessing scalability, data modeling, and system compatibility.

Ph.D.

Virginia Tech

Computer Engineering

• GPA: 3.74 / 4.00
• Thesis: Enhancing Software Security through Code Diversification Verification, Control-flow Restriction, and Automatic Compartmentalization
• Research focus: software verification, control-flow integrity, and automated compartmentalization.

M.S.

University of South Florida

Computer Engineering

• GPA: 3.76 / 4.00
• Thesis: Security of Non-Volatile Memories — Attack Models, Analyses, and Counter-Measures
• Research focus: spintronics-based memory security.

B.S.

University of South Florida

Computer Engineering

• GPA: 3.69 / 4.00